Influence of HALO and source/drain implantation on threshold voltage in 45nm PMOS device

In this paper, we investigate the influence of process parameters like HALO and Source/Drain (S/D) Implantation on threshold voltage in 45nm PMOS device. The settings of process parameters were determined by using Taguchi experimental design method. The level of importance of the process parameters on threshold voltage was determined by using analysis of variance (ANOVA). The virtual fabrication of the PMOS device was performed by using ATHENA module. While the electrical characterization of the device was implemented by using ATLAS module. These two modules were combined with Taguchi method to aid in design and optimizer the process parameters. Besides HALO and S/D implantation, the other two process parameters which used were oxide growth temperature and silicide anneal temperature. These process parameters were varied for 3 levels to perform 9 experiments. Threshold voltage (VTH) results were used as the evaluation variables. Then, the results were subjected to the Taguchi method to determine the optimal process parameters and to produce predicted values. The predicted values of the process parameters were verified successfully with ATHENA and ATLAS's simulator. In this research, halo implantation found to be the major factor affecting the threshold voltage (70%), whereas silicide anneal temperature was the second ranking factor (17%). As conclusions, halo implantation was identified as one of the process parameters that has the strongest effect on the response characteristics. While the S/D Implantation was identified as an adjustment factor to get the threshold voltage closer to the nominal value (-0.150V)

Configurations of memristor-based APUF for improved performance

The memristor-based arbiter PUF (APUF) has great potential to be used for hardware security purposes. Its advantage is in its challenge-dependent delays, which cannot be modeled by machine learning algorithms. In this paper, further improvement is proposed, which are circuit configurations to the memristor-based APUF. Two configuration aspects were introduced namely varying the number of memristor per transistor, and the number of challenge and response bits. The purpose of the configurations is to introduce additional variation to the PUF, thereby improve PUF performance in terms of uniqueness, uniformity, and bit-aliasing; as well as resistance against support vector machine (SVM). Monte Carlo simulations were carried out on 180 nm and 130 nm, where both CMOS technologies have produced uniqueness, uniformity, and bit-aliasing values close to the ideal 50%; as well as SVM prediction accuracies no higher than 52.3%, therefore indicating excellent PUF performance

Optimization of HALO structure effects in 45nm p-type MOSFETs device using Taguchi Method

In this study, the Taguchi method was used to optimize the effect of HALO structure or halo implant variations on threshold voltage (VTH) and leakage current (ILeak) in 45nm p-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) device. Besides halo implant dose, the other process parameters which used were Source/Drain (S/D) implant dose, oxide growth temperature and silicide anneal temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to VTH and ILeak are halo implant dose (40%) and S/D implant dose (52%) respectively. Whereas the second ranking factor affecting VTH and ILeak are oxide growth temperature (32%) and halo implant dose (34%) respectively. The results show that after optimizations approaches is -0.157V at ILeak=0.195mA/μm

Architectural synthesis of analogue filters from behavioural VHDL-AMS descriptions

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Architectural synthesis of analogue filters from behavioural VHDL-AMS descriptions

The primary aim of this research is to investigate and develop techniques for VHDL-AMS-based synthesis of analogue filters suitable for use in mixed-signal ASICs where behavioural models are especially important. Particular emphasis is put on architectural optimisation with the aim to identify the most suitable circuit topologies. The novel contributions can be briefly summarised as follows. New methods have been presented to extract synthesisable VHDL-AMS constructs from behavioural filter models using parse trees. They can be extended to support a more general, mixed-signal synthesis system based on VHDL-AMS. An effective architectural optimisation engine for analogue filter synthesis has been developed to minimise transfer function accuracy errors and power consumption. The engine is based on three-tier architectural and parametric optimisation, in which a combination of heuristic and systematic search algorithms provides a possibility of global optimisation. The parametric optimiser relies on full HSPICE simulation to ensure accurate circuit performance evaluation. The new methods are implemented in a demonstrator system named FIST (Filter Synthesis Tool), and were successfully applied to several case studies of 1 GHz integrated analogue filter circuits designed for implementation in a 0.35μm CMOS technology. The method of using parse trees to extract circuit-level structures from high-level descriptions proved to be effective. It was shown that parse trees allow for easy detection of synthesisable constructs and support recursive static evaluations of expressions necessary in calculation of filter parameters. This technique provides a groundwork from which more general VHDL-AMS-based synthesis systems can be developed.</p

Prospective Efficient Ambient Energy Harvesting Sources for IoT-Equipped Sensor Applications

In the past few years, the internet of things (IoT) has garnered a lot of attention owing to its significant deployment for fulfilling the global demand. It has been seen that power-efficient devices such as sensors and IoT play a significant role in our regular lives. However, the popularity of IoT sensors and low-power electronic devices is limited due to the lower lifetime of various energy resources which are needed for powering the sensors over time. For overcoming this issue, it is important to design and develop better, high-performing, and effective energy harvesting systems. In this article, different types of ambient energy harvesting systems which can power IoT-enabled sensors, as well as wireless sensor networks (WSNs), are reviewed. Various energy harvesting models which can increase the sustainability of the energy supply required for IoT devices are also discussed. Furthermore, the challenges which need to be overcome to make IoT-enabled sensors more durable, reliable, energy-efficient, and economical are identified